用Verilog语言写的三_五分频电路.doc

用 Verilog 语言写的三分频电路方法一： /上升沿触发的分频设计 module three(clkin, clkout); input clkin;/ 定义输入端口 output clkout;/ 定义输出端 ? reg 1:0 step1, step; always (posedge clkin) begin case (step) 2'b00: step<=2'b01; 2'b01: step<=2'b10; 2'b10: step<=2'b00; default :step<=2'b00;endcase end always (negedge clkin) begin case (step1) 2'b00: step1<=2'b01; 2'b01: step1<=2'b10; 2'b10: step1<=2'b00; default :step1<=2'b00;endcase end assign clkout=(step1|step11); endmodule方法二：clock, 第三个周期输出低这样/ 如果 duty cycle =50%, 可以第一个周期第二个周期输出原先 可以实现三分频，输出是占空比 1:1 的三分频 .module three(clk,throut) ; input clk ;output throut;reg q1,q2,d,throut; always (posedge clk) if(!d) q1=1'b1;else q1=q1 ; always (negedge clk) if(!d) q2=1'b1;else q2=q2 ;always (q1 or q2) d=q1&q2 ;50：always (posedge d) throut=throut; endmodule 用 Verilog 语言写五分频电路，占空比为 module div_5 ( clkin,rst,clkout );input clkin,rst; output clkout; reg 2:0 step1, step2;always (posedge clkin ) if(!rst) step1<=3'b000;else begin case (step1) 3'b000: step1<=3'b001;3'b001: step1<=3'b011;3'b011: step1<=3'b100;3'b100: step1<=3'b010;3'b010: step1<=3'b000; default:step1<=3'b000;endcase end always (negedge clkin ) if(!rst) step2<=3'b000;else begin case (step2) 3'b000: step2<=3'b001;3'b001: step2<=3'b011;3'b011: step2<=3'b100;3'b100: step2<=3'b010;3'b010: step2<=3'b000; default:step2<=3'b000;endcase end assign clkout=step10|step20; endmodule