VHDL交通灯.doc
实 验 报 告课程名称：EDA课程设计实验名称:交通控制器的设计专业班级： 学生姓名： 学号： 指导老师： 实验日期：2012/12/15一、实验目的掌握VHDL状态机设计。二、实验内容设计一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器，具体要求如下： (1) 主、支干道各设有一个绿、黄、红指示灯，两个显示数码管。 (2)主、支道交替允许通行，主干道每次放行45 s，支干道每次放行25 s，在每次由亮绿灯变成亮红灯的转换过程中，要亮5 s的黄灯作为过渡，并进行减计时显示。 三、设计（实验）正文 实验时使用状态机完成对交通灯的控制，设置s0,s1,s2,s3四个状态，分别表示主绿支红，主黄支红，主红支绿，主红支黄四个状态，设置LED1,LED2,LED3,LED4四个输出来控制倒计时数码管工作。同时使用计数器对交通灯进行时间控制。四、设计（实验）编码library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity traffic isport (clk:in std_logic; lgt1_red, lgt1_yellow,lgt1_green:out std_logic; -主干道的红黄绿灯 lgt2_red,lgt2_yellow,lgt2_green:out std_logic;-支干道的红 黄绿灯 led1:out std_logic_vector(6 downto 0); led2:out std_logic_vector(6 downto 0); led3:out std_logic_vector(6 downto 0); led4:out std_logic_vector(6 downto 0) ); end entity traffic;architecture rtl of traffic istype states is (s0,s1,s2,s3); -4种状态signal one1,ten1,one2,ten2:std_logic_vector(3 downto 0); -倒计时的个位和十位signal qh1,ql1,qh2,ql2:std_logic_vector (3 downto 0);-数码管地址控制信号bcdsignal ra,rb,ga,gb,ya,yb:std_logic;beginprocess(clk)variable m:states :=s0;variable a :std_logic;variable qh1,ql1,qh2,ql2:std_logic_vector(3 downto 0);-计位的高位和低位beginif clkevent and clk=1 thenif(m=s0)then if a=0 then -状态s1，主干道通行45sqh1:="0100" -高位为4ql1:= "0100" -低位为4 0-44ql2:="1001"qh2:="0100" -49sa:=1;ra<=0;ya<=0;ga<=1; -主干道绿灯亮rb <=1; -支干道红灯亮yb<=0;gb<=0;else if qh1 =0 and ql1 =1 then -如果倒计时到01结束，则转到s1的状态m:=s1;a:=0; -使能ql1:=ql1-1; - 变为0ql2:=ql2-1; -此时相应的ql2减1elsif ql1=0 then -倒计时45s 个位为0ql1:="1001"qh1:=qh1-1;ql2:=ql2-1; - 跟ql1同时减1elsif ql2=0 thenql2:="1001"qh2:=qh2-1;ql1:=ql1-1; -再由0变为9的过程 qh2减1，ql1相应减1else ql1:=ql1-1;ql2:=ql2-1;end if;end if ; -状态s1，转干道黄灯倒计时5selsif(m=s1)then if a=0 then ql1:="0100"qh1:="0000" -高位为4 0-4a:=1;ra<=0;ya<=1; -主干道黄灯点亮ga<=0;rb <=1; -支干道红灯点亮yb<=0;gb<=0;ql2:=ql2-1; -此时减1 这样同ql1 差1 selseif ql1=1 then -如果倒计时结束，则转到s2 状态m:=s2;a:=0;qh1:="0000"ql1:="0000"ql2:=ql2-1;elsif ql2=1 then ql2:="0000" qh2:="0000" ql1:=ql1-1; -倒计时没结束 低位为1时 elseql1:=ql1-1;ql2:=ql2-1;end if;end if; -状态s2 ，支干道通行25selsif(m=s2)then if a =0 then ql2:= "0100" -低位为4qh2:= "0010" -高位为2ql1:= "1001"qh1:= "0010" -29sa:=1;ra<=1; -主干道红灯点亮ya<=0;ga<=0;rb<=0;yb<=0;gb<=1; -支干道绿灯亮else if qh2 = 0 and ql2 =1 then -如果倒计时结束，则转到s3m:=s3;a:=0;qh2:="0000"ql2:="0000"ql1:=ql1-1;elsif ql1=0 then ql1:="1001" qh1:=qh1-1; ql2:=ql2-1;elsif ql2=0 then - 实现倒计时25 sql2:="1001"qh2:=qh2-1;ql1:=ql1-1;elseql2:=ql2-1;ql1:=ql1-1;end if;end if ; -状态s3，支干道黄灯倒计时5selsif(m=s3)then if a=0 then qh2:="0000" -高位为0ql2:="0100" -低位为4a:=1;ra<=1; -主干道红灯亮ya<=0;ga<=0;rb<=0;yb <=1; -支干道绿灯亮gb<=0;ql1:=ql1-1;else if ql2=1 then -如果倒计时结束，则转到s1状态m:=s0;a:=0;qh2:="0000"ql2:="0000"ql1:=ql1-1;elsif ql1=1 then ql1:="0000" qh1:="0000" ql2:=ql2-1; elseql2:=ql2-1;ql1:=ql1-1;end if ;end if;end if;one1 <=ql1;ten1 <=qh1;one2 <=ql2;ten2 <=qh2; end if ; end process;process(clk,ra,rb,ga,gb,ya,yb)begin lgt1_red<=ra;lgt2_red<=rb;lgt1_green<=ga;lgt2_green<=gb;lgt1_yellow<=ya;lgt2_yellow<=yb;end process;process(ten1,ten2,one1,one2) isbegincase ten1 is when"0000"=>led1<="0111111"when"0001"=>led1<="0000110"when"0010"=>led1<="1011011"when"0011"=>led1<="1001111"when"0100"=>led1<="1100110"when"0101"=>led1<="1101101"when"0110"=>led1<="1111101"when"0111"=>led1<="0000111"when"1000"=>led1<="1111111"when "1001"=>led1<="1101111"when others=> led1<="0000000"end case; case one1 is when"0000"=>led2<="0111111"when"0001"=>led2<="0000110"when"0010"=>led2<="1011011"when"0011"=>led2<="1001111"when"0100"=>led2<="1100110"when"0101"=>led2<="1101101"when"0110"=>led2<="1111101"when"0111"=>led2<="0000111"when"1000"=>led2<="1111111"when "1001"=>led2<="1101111"when others=> led2<="0000000"end case; case ten2 is when"0000"=>led3<="0111111"when"0001"=>led3<="0000110"when"0010"=>led3<="1011011"when"0011"=>led3<="1001111"when"0100"=>led3<="1100110"when"0101"=>led3<="1101101"when"0110"=>led3<="1111101"when"0111"=>led3<="0000111"when"1000"=>led3<="1111111"when "1001"=>led3<="1101111"when others=> led3<="0000000"end case; case one2 is when"0000"=>led4<="0111111"when"0001"=>led4<="0000110"when"0010"=>led4<="1011011"when"0011"=>led4<="1001111"when"0100"=>led4<="1100110"when"0101"=>led4<="1101101"when"0110"=>led4<="1111101"when"0111"=>led4<="0000111"when"1000"=>led4<="1111111"when "1001"=>led4<="1101111"when others=> led4<="0000000"end case; end process; end architecture rtl;五、设计（实验）的波形六、实验心得 通过本次课程设计，对于VHDL语句有了更深一层的理解，理论与实践相结合，提高了自己的动手能力，对于知识的理解上升了一个新的阶段，提高了解决问题的能力，对于本专业有了更深层次的了解。
