keil调试环境下S3C2440.s的分析.doc

.; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs ;向量中断模式/非向量中断模式设置;通过PSRs（程序状态寄存器）来设置; 系统工作模式设定; CPSR是当系统前程序状态寄存器，SPSR是备份程序状态寄存器。其中CPSR共用一个物理寄存器，而SPSR一共有5个物理寄存器; CPSR寄存器设定：CPSR4.0 为M4-M0，通过它可以设定处理器的工作模式Mode_USR EQU 0x10 ; 用户模式Mode_FIQ EQU 0x11 ; 快速中断模式Mode_IRQ EQU 0x12 ; 外部中断模式Mode_SVC EQU 0x13 ; 超级用户模式Mode_ABT EQU 0x17 ; 数据访问终止模式Mode_UND EQU 0x1B ; 未定义指令终止模式Mode_SYS EQU 0x1F ; 系统模式I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled 外部中断屏蔽位，置1，关闭中断，置0，打开中断F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled 快速中断屏蔽位，置1，关闭中断，置0，打开中断;- Stack and Heap Definitions -;/ <h> Stack Configuration (Stack Sizes in Bytes);/ <o0> Undefined Mode <0x0-0xFFFFFFFF:8>/ <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>/ <o2> Abort Mode <0x0-0xFFFFFFFF:8>/ <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>/ <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>精品.;/ <o5> User/System Mode <0x0-0xFFFFFFFF:8>/ </h> 栈配置，系统的栈空间设定UND_Stack_Size EQU 0x00000000 ; 未定义模式的栈大小SVC_Stack_Size EQU 0x00000008 ; 超级用户模式的栈大小ABT_Stack_Size EQU 0x00000000 ; 数据访问终止模式的栈大小FIQ_Stack_Size EQU 0x00000000 ; 快速中断模式的栈大小IRQ_Stack_Size EQU 0x00000080 ; 外部中断模式的栈大小USR_Stack_Size EQU 0x00000400 ; 用户模式的栈大小ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) ; 所有模式的堆栈相加得到总堆栈的大小; ARM的汇编程序由段组成，段是相对独立的指令或数据单位，每个段由AREA伪指令定义，并定义段的属性。-READWRITE（读写）、READONLY（只读） AREA STACK, NOINIT, READWRITE, ALIGN=3 ; 开辟一个堆栈段，段名字为STACK，定义为可读可写，; 不初始化内存单元，或将内存单元初始化为0Stack_Mem SPACE USR_Stack_Size ; _initial_sp SPACE ISR_Stack_Size ; 汇编代码的地址标号Stack_Top ; 堆栈段内容结束， 在这里放个标号,用来获得堆栈顶部地址;/ <h> Heap Configuration;/ <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>/ </h>精品.Heap_Size EQU 0x00000000 ; 堆大小设置 AREA HEAP, NOINIT, READWRITE, ALIGN=3 ; 开辟一个段，名字为HEAP可读可写，不初始化内存单元，或者初始化为0_heap_baseHeap_Mem SPACE Heap_Size_heap_limit;- Memory Definitions -; Internal Memory Base Addresses ; 片上SRAM的基地址，即内存基地址IRAM_BASE EQU 0x40000000;- Watchdog Timer Definitions -WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address 看门狗定时器基地址WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset 看门狗控制寄存器偏移地址，相对于基址WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset 看门狗数据寄存器偏移地址，相对于基址WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset 看门狗计数寄存器偏移地址，相对于基址;/ <e> Watchdog Timer Setup;/ <h> Watchdog Timer Control Register (WTCON);/ <o1.8.15> Prescaler Value <0-255>/ <o1.5> Watchdog Timer Enable;/ <o1.3.4> Clock Division Factor;/ <0=> 16 <1=> 32 <2=> 64 <3=> 128;/ <o1.2> Interrupt Generation Enable精品.;/ <o1.0> Reset Enable;/ </h>/ <h> Watchdog Timer Data Register (WTDAT);/ <o2.0.15> Count Reload Value <0-65535>/ </h>/ </e> Watchdog Timer SetupWT_SETUP EQU 1 ; 看门狗设置WTCON_Val EQU 0x00000000 ; 看门狗控制寄存器设置，关闭看门狗WTDAT_Val EQU 0x00008000 ; 看门狗数据寄存器设置，初始值即为0x8000;- Clock and Power Management Definitions -CLOCK_BASE EQU 0x4C000000 ; Clock Base Address ; 时钟基地址LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset ; 锁相环锁定时间计数寄存器偏移地址，相对于基址MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset ; MPLL配置寄存器偏移地址，相对于基址，主时钟源PLLUPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset ; UPLL配置寄存器偏移地址，相对于基址，USB时钟源PLLCLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset ; 时钟控制寄存器偏移地址，相对于基址CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset ; 时钟减慢控制寄存器偏移地址，相对于基址CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset ; 时钟分频器控制寄存器偏移地址，相对于基址CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset ; 摄像头时钟分频器控制寄存器偏移地址，相对于基址，UPLL提供精品.;/ <e> Clock Setup;/ <h> PLL Lock Time Count Register (LOCKTIME);/ <o1.16.31> U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF>/ <o1.0.15> M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF>/ </h>/ <h> MPLL Configuration Register (MPLLCON);/ <i> MPLL = (2 * m * Fin) / (p * 2s);/ <o2.12.19> m: Main Divider m Value <9-256><#-8>/ <i> m = MDIV + 8;/ <o2.4.9> p: Pre-divider p Value <3-64><#-2>/ <i> p = PDIV + 2;/ <o2.0.1> s: Post Divider s Value <0-3>/ <i> s = SDIV ;/ </h>/ <h> UPLL Configuration Register (UPLLCON);/ <i> UPLL = ( m * Fin) / (p * 2s);/ <o3.12.19> m: Main Divider m Value <8-263><#-8>/ <i> m = MDIV + 8;/ <o3.4.9> p: Pre-divider p Value <2-65><#-2>/ <i> p = PDIV + 2;/ <o3.0.1> s: Post Divider s Value <0-3>/ <i> s = SDIV 精品.;/ </h>/ <h> Clock Generation Control Register (CLKCON);/ <o4.20> AC97 Enable;/ <o4.19> Camera Enable;/ <o4.18> SPI Enable;/ <o4.17> IIS Enable;/ <o4.16> IIC Enable;/ <o4.15> ADC + Touch Screen Enable;/ <o4.14> RTC Enable;/ <o4.13> GPIO Enable;/ <o4.12> UART2 Enable;/ <o4.11> UART1 Enable;/ <o4.10> UART0 Enable;/ <o4.9> SDI Enable;/ <o4.8> PWMTIMER Enable;/ <o4.7> USB Device Enable;/ <o4.6> USB Host Enable;/ <o4.5> LCDC Enable;/ <o4.4> NAND FLASH Controller Enable;/ <o4.3> SLEEP Enable;/ <o4.2> IDLE BIT Enable;/ </h>精品.;/ <h> Clock Slow Control Register (CLKSLOW);/ <o5.7> UCLK_ON: UCLK ON;/ <o5.5> MPLL_OFF: Turn off PLL;/ <o5.4> SLOW_BIT: Slow Mode Enable;/ <o5.0.2> SLOW_VAL: Slow Clock Divider <0-7>/ </h>/ <h> Clock Divider Control Register (CLKDIVN);/ <o6.3> DIVN_UPLL: UCLK Select;/ <0=> UCLK = UPLL clock;/ <1=> UCLK = UPLL clock / 2;/ <o6.1.2> HDIVN: HCLK Select;/ <0=> HCLK = FCLK;/ <1=> HCLK = FCLK / 2;/ <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8;/ <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6;/ <o6.0> PDIVN: PCLK Select;/ <0=> PCLK = HCLK;/ <1=> PCLK = HCLK / 2;/ </h>/ <h> Camera Clock Divider Control Register (CAMDIVN);/ <o7.12> DVS_EN: ARM Core Clock Select;/ <0=> ARM core runs at FCLK精品.;/ <1=> ARM core runs at HCLK;/ <o7.9> HCLK4_HALF: HDIVN Division Rate Change Bit;/ <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4;/ <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8;/ <o7.8> HCLK3_HALF: HDIVN Division Rate Change Bit;/ <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3;/ <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6;/ <o7.4> CAMCLK Select;/ <0=> CAMCLK = UPLL;/ <1=> CAMCLK = UPLL / CAMCLK_DIV;/ <o7.0.3> CAMCLK_DIV: CAMCLK Divider <0-15>/ <i> Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1);/ <i> Divider is used only if CAMCLK_SEL = 1;/ </h>/ </e> Clock SetupCLOCK_SETUP EQU 0 ; 时钟设置LOCKTIME_Val EQU 0x0FFF0FFF ; PLL锁定时间计数器值MPLLCON_Val EQU 0x00043011 ; MPLL配置寄存器值UPLLCON_Val EQU 0x00038021 ; UPLL配置寄存器值CLKCON_Val EQU 0x001FFFF0 ; 时钟配置寄存器值CLKSLOW_Val EQU 0x00000004 ; 时钟减慢控制寄存器值CLKDIVN_Val EQU 0x0000000F ; 时钟分频控制寄存器值精品.CAMDIVN_Val EQU 0x00000000 ; 摄像头分频控制寄存器值;- Memory Controller Definitions -; 存储控制器设置MC_BASE EQU 0x48000000 ; Memory Controller Base Address ; 存储控制器基地址BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset ; 总线宽度和等待控制寄存器BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset ; BANK0-BOOT ROM控制寄存器设置BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset ; BANK1BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset ; BANK2BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset ; BANK3BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset ; BANK4BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset ; BANK5BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset ; BANK6BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset ; BANK7REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset ; DRAM/SDRAM刷新控制BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset ; 可调的bank大小寄存器MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset ; 模式控制寄存器bank6MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset ; 模式控制寄存器bank7;/ <e> Memory Controller Setup;/ <h> Bus Width and Wait Control Register (BWSCON);/ <o1.31> ST7: Use UB/LB for Bank 7;/ <o1.30> WS7: Enable Wait Status for Bank 7精品.;/ <o1.28.29> DW7: Data Bus Width for Bank 7;/ <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved;/ <o1.27> ST6: Use UB/LB for Bank 6;/ <o1.26> WS6: Enable Wait Status for Bank 6;/ <o1.24.25> DW6: Data Bus Width for Bank 6;/ <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved;/ <o1.23> ST5: Use UB/LB for Bank 5;/ <o1.22> WS5: Enable Wait Status for Bank 5;/ <o1.20.21> DW5: Data Bus Width for Bank 5;/ <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved;/ <o1.19> ST4: Use UB/LB for Bank 4;/ <o1.18> WS4: Enable Wait Status for Bank 4;/ <o1.16.17> DW4: Data Bus Width for Bank 4;/ <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved;/ <o1.15> ST3: Use UB/LB for Bank 3;/ <o1.14> WS3: Enable Wait Status for Bank 3;/ <o1.12.13> DW3: Data Bus Width for Bank 3;/ <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved;/ <o1.11> ST2: Use UB/LB for Bank 2;/ <o1.10> WS2: Enable Wait Status for Bank 2;/ <o1.8.9> DW2: Data Bus Width for Bank 2;/ <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved精品.;/ <o1.7> ST1: Use UB/LB for Bank 1;/ <o1.6> WS1: Enable Wait Status for Bank 1;/ <o1.4.5> DW1: Data Bus Width for Bank 1;/ <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved;/ <o1.1.2> DW0: Indicate Data Bus Width for Bank 0;/ <1=> 16-bit <2=> 32-bit;/ </h>/ <h> Bank 0 Control Register (BANKCON0);/ <o2.13.14> Tacs: Address Set-up Time before nGCS;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o2.11.12> Tcos: Chip Selection Set-up Time before nOE;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o2.8.10> Tacc: Access Cycle;/ <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks;/ <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks;/ <o2.6.7> Tcoh: Chip Selection Hold Time after nOE;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o2.4.5> Tcah: Address Hold Time after nGCS;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o2.2.3> Tacp: Page Mode Access Cycle at Page Mode;/ <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks;/ <o2.0.1> PMC: Page Mode Configuration精品.;/ <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data;/ </h>/ <h> Bank 1 Control Register (BANKCON1);/ <o3.13.14> Tacs: Address Set-up Time before nGCS;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o3.11.12> Tcos: Chip Selection Set-up Time before nOE;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o3.8.10> Tacc: Access Cycle;/ <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks;/ <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks;/ <o3.6.7> Tcoh: Chip Selection Hold Time after nOE;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o3.4.5> Tcah: Address Hold Time after nGCS;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o3.2.3> Tacp: Page Mode Access Cycle at Page Mode;/ <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks;/ <o3.0.1> PMC: Page Mode Configuration;/ <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data;/ </h>/ <h> Bank 2 Control Register (BANKCON2);/ <o4.13.14> Tacs: Address Set-up Time before nGCS;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks精品.;/ <o4.11.12> Tcos: Chip Selection Set-up Time before nOE;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o4.8.10> Tacc: Access Cycle;/ <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks;/ <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks;/ <o4.6.7> Tcoh: Chip Selection Hold Time after nOE;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o4.4.5> Tcah: Address Hold Time after nGCS;/ <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks;/ <o4.2.3> Tacp: Page Mode Access Cycle at Page Mode;/ <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks;/ <o4.0.1> PMC: Page Mode Configuration;/ <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data;/ </h>