TSMC0.25和0.35um设计规则.docx
《TSMC0.25和0.35um设计规则.docx》由会员分享,可在线阅读,更多相关《TSMC0.25和0.35um设计规则.docx(20页珍藏版)》请在三一文库上搜索。
1、2设计规则设计规则几何关系定义Width:Sapcing:Extension : 一几何图形内边界到另一图形外边界长度Overlap : 一几何图形内边界到另一图形内边界长度2.2设计规则4M2 lambda =5Mlambda =2.2.1 Well PjvrdlDescriptionSUBMDEEPMinimum width1212Minimum spacing between wells at different potential1818Minimum spacing between wells at same potential66Minimum spacing between we
2、lls of different type002.2.2 Active DescriptionSUBMDEEPMinimum width33Minimum spacing33Source/drain active to well edge66Substrate/well contact active to well edge33Minimum spacing between active of different implant442.2.3 Thick Active is a layer used for those processes offering two differentthick
3、nesses of gate oxide (typically for the layout of transistors that operate at two different voltage levels). The ACTIVE layer is used to delineate all the active areas, regardless of gateoxide thickness. THICK_ACTIVE is used to to mark those ACTIVE areas that will have the thicker gate oxide; ACTIVE
4、 areas outside THICK_ACTIVE will have the thinner gate oxide.RuleDescriptionSUBMDEEPMinimum width44Minimum spacing44Minimum ACTIVE overlap44Minimum space to external ACTIVE44Minimum poly width in a THICK_ACTIVE gate332.2.4 Poly nDescriptionSUBMDEEPMinimum width22Minimum spacing over field33Minimum s
5、pacing over active34Minimum gate extension of active2Minimum active extension of poly34Minimum field poly to active113.5Poly-3.33.4Active2.2.5 Silicide Block 口1pSB width4Minimum SB spacing4Minimum spacing, SB to contact (no contacts allowed inside SB)2Minimum spacing, SB to external active口uMinimum
6、spacing, SB to external poly2Resistor is poly inside SB; poly ends stick out for contacts the entire resistor must be outside well and over fieldN/ApMinimum poly width in resistor5Minimum spacing of poly resistors (in a single SB region)71 Minimum SB overlap of poly22.2.6 Select pDescriptionSUBMDEEP
7、Minimum select spacing to channel of transistor33Minimum select overlap of active22Minimum select overlap of contact1Minimum select width and spacing (Note: P-select and N-selectmay be coincident, but mustnot overlap)24active电A史JiThe same rules apply with N+ Seled and P+_Select reverwd .2.2.7 Electr
8、ode for Capacitor poly2 layer is a second polysilicon layer (physically above the standard, or first, poly layer). The oxide between the two polysis the capacitor dielectric. The capacitor area is the area of coincident poly and electrode.RuleDescriptionSUBMDEEPMinimum width7Minimum spacing3Minimum
9、poly overlap5n/aMinimum spacing to active or well edge (not 川ustrated)2Minimum spacing to poly contact6Minimum spacing to unrelated metal22.2.8 Electrode Contact poly2 is contacted through the standardcontact layer, similar to the first poly. The overlap numbers are larger, however.1RulerDescription
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- TSMC0 25 0.35 um 设计 规则
链接地址:https://www.31doc.com/p-14040587.html